1. Field of Technology
Embodiments disclosed herein relate generally to a gate driver system architecture and control scheme, and more specifically, to a gate driver system that dynamically adjusts drive current during a single switching cycle.
2. Description of the Related Arts
A power metal-oxide-semiconductor field-effect transistor (MOSFET) is a commonly used semi-conductor switching device in power electronics systems including switching-mode power supplies. The gate driver for the power MOSFET is critical to achieving high performance, such as low electro-magnetic interference (EMI), high efficiency and good control performance. FIG. 1 is a circuit diagram illustrating a conventional flyback type switching power converter 100 that uses a MOSFET Q1. The switching power converter 100 includes a power stage 105 and a secondary output stage 107. Power stage 105 includes the MOSFET Q1 and a power transformer T1. Power transformer T1 includes primary winding Np, secondary winding Ns, and auxiliary winding Na. Secondary output stage 107 includes diode D1 and output capacitor C1. Controller 101 controls the ON state and the OFF state of MOSFET Q1 using output drive signal 102 in the form of a pulse with on-times (TON) and off-times (TOFF). In other words, the controller 101 generates the output drive signal 102 that drives the MOSFET Q1.
AC power is received from an AC power source (not shown) and is rectified to provide the unregulated input voltage VDC. The input power is stored in transformer T1 while the switch Q1 is turned on, because the diode D1 becomes reverse biased when the MOSFET Q1 is turned on. The rectified input power is then transferred to an electronic device across the capacitor C1 while the switch Q1 is turned off, because the diode D1 becomes forward biased when the MOSFET Q1 is turned off. Diode D1 functions as an output rectifier and capacitor C1 functions as an output filter. The resulting regulated output voltage VOUT is delivered to the electronic device.
As mentioned previously, the controller 101 generates appropriate switch drive pulses 102 to control the on-times and off-times of MOSFET Q1 and regulate the output voltage VOUT. The controller 101 controls MOSFET Q1 using a feedback loop based on the sensed output voltage VSENSE and the sensed primary side current ID in previous switching cycles of the switching power converter, in a variety of operation modes including PWM (pulse width modulation) and/or PFM (pulse frequency modulation) modes. ISENSE is used to sense the primary current ID through the primary winding Np and switch Q1 in the form of a voltage across sense resistor RS.
The output voltage VOUT is reflected across auxiliary winding Na of transformer T1, which is input to controller 101 as the voltage VSENSE via a resistive voltage divider comprised of resistors R1 and R2. Based on the sensed output voltage, the controller 101 determines the operating frequency of the switching power converter 100 which dictates the frequency of the on-times (TON) and off-times (TOFF) in the output drive signal 102.
FIG. 2 illustrates a conventional gate driver system configuration included in the controller 101. The driver final stage comprises a high-side PMOS QP and a low-side NMOS QN. The high-side PMOS source is connected to Vcc, and the low-side NMOS source is connected to ground (GND). As shown in FIG. 2, the controller 101 comprises a gate driver control circuit 201. The gate driver control circuit 201 generates a switch control signal S, and the driver signals Sp and SN respectively for the PMOS QP and the NMOS QN.
FIG. 3 illustrates an equivalent circuit model often used for the analysis of MOSFET switching performance. The switching performance of a device is determined by the time required to establish voltage changes across parasitic capacitances of the device. RG represents the distributed resistance of the gate of the MOSFET. LS and LD respectively represent the source and drain lead inductances of the MOSFET. CGD represents the gate-to-drain capacitance (i.e., the miller capacitance) of the MOSFET and is a nonlinear function of voltage. CGS and CDS respectively represent the gate-to-source capacitance and the drain-to-source capacitance of the MOSFET. Lastly, the equivalent circuit model illustrates the body-drain diode across the drain and source of the MOSFET.
The MOSFET operation can be understood referring to detailed waveforms illustrated in FIG. 4. Generally, FIG. 4 illustrates the current ISENSE which corresponds to the drain current ID of the power MOSFET Q1, the switch control signal S, the gate driver signal SN for the driver low-side NMOS QN, the gate driver signal SP for the driver high-side PMOS QP, the gate-to-source voltage VGS of the MOSFET Q1, and the drain-to-source voltage VDS of the MOSFET Q1 at various times within a switching cycle.
At time t0, the controller 101 turns on Q1 by issuing a high 401 switch control signal S and turns off the low-side NMOS QN by issuing a low 403 gate driver signal SN. At time t1, after a short-time delay that prevents shoot through between the high-side PMOS QP and low-side NMOS QN, the controller 101 sets the gate driver signal SP to low 405 which turns on the high-side PMOS QP. During the time interval [t1, t2], the gate drive current charges the input capacitor of Q1. The current flows through the high-side PMOS QP, and the on-state resistance Rds(on)_P of the high-side PMOS QP serves as the gate resistance Rg that affects the drive current used to drive power MOSFET Q1. When the gate-to-source voltage VGS of Q1 rises 407 above the threshold voltage VTH for MOSFET Q1, Q1 starts to conduct. During the time interval [t1, t2], the drain-to-source voltage VDS of MOSFET Q1 still maintains high voltage 409, e.g., VDS=VDC. VDC can be ˜300V or higher depending on the system configuration.
During the time interval [t2, t3], the gate-to-source voltage VGS of Q1 reaches a plateau 411 and stays at this plateau 411. Furthermore, the drive current mainly charges the miller capacitor CGD of Q1. As shown in FIG. 4, the drain-to-source voltage VDS of Q1 decreases 413 during time interval [t2, t3] represented by dV/dt. The rate of change dV/dt of the drain-to-source voltage VDS of Q1 coupled with the drain-to-source capacitor CDS of Q1 and the parasitic capacitance of the transformer generates the current spike 415 in the drain current ID by means of C*dV/dt. During the time interval [t3, t4], when the drain-to-source voltage VDS of Q1 decreases to a low level 417, the miller capacitor CGD is fully charged, and the drive current mainly charges the gate-to-source capacitor CGS of Q1. During the time interval [t3, t4], the gate-to-source voltage VGS rises 419 and eventually reaches near VCC. The turn-on transition of Q1 is completed. During the time interval [t4, t5], the gate-to-source voltage VGS is maintained near VCC and the drain-to-source voltage VDS of Q1 remains at the low level 417. Furthermore, during the time interval [t4, t5], the drain current ID rises 421 towards the ideal peak.
At time t5, the controller 101 decides to turn-off Q1 shown by the switch control signal S going low 423, and the gate driver signal Sp is set high 425 which turns off the high-side PMOS QP. As shown in FIG. 4, the drain current ID reaches the ideal peak at time t5. At time t5, the gate driver signal SN remains low 403. Furthermore, at time t5 the gate-to-source voltage VGS is maintained near VCC and the drain-to-source voltage VDS of Q1 remains at the low level 417.
At time t6, after a short time delay that prevents the shoot through between the high side PMOS QP and the low side NMOS QN, the gate driver signal SN is set to high 427 which turns on the low side NMOS QN. During time interval [t6, t7], the low side NMOS QN provides the path to discharge capacitor CGS, and the on-state resistance Rds(on)_N of the low side NMOS QN affects the discharge current. As shown in FIG. 4, the gate-to-source voltage VGS of Q1 decreases 429 from VCC to a plateau 431 that is less than VCC but greater than VTH and the drain-to-source voltage VDS of Q1 stays at the low level 417.
During the time interval [t7, t8], the gate-to-source voltage VGS of Q1 remains at the plateau 431 and the drive current mainly discharges the miller capacitor CGD of Q1. Furthermore, the drain-to-source voltage VDS rises 433 towards the high voltage 409 during the time interval [t7, t8] which is represented by dV/dt. During the time interval [t8, t9], (without considering high-frequency ringing and other parasitic effects) the drain-to-source voltage VDS of Q1 reaches the maximum DC voltage 409 and the drive current mainly discharge the capacitor CGS. Furthermore, the gate-to-source voltage VGS of Q1 decreases 435. Once the gate-to-source voltage VGS decreases below the threshold voltage VTH, Q1 is turned off and the drain current ID reaches the actual peak at time t9 and decays 437 to zero. The turn-off transition of the Q1 is completed.